Embodiments of the present invention generally relate to switches for data-communication networks, and more specifically, to switches for telecommunication networks being reconfigurable to operate in a plurality of modes.
Telecommunication switches are typically utilized in networks for directing data through circuits which comprise the network. Switches normally have a plurality of inputs and a corresponding number of outputs, so data entering any input line may be routed to any output line. Ideally, the switching function would be performed with one single monolithic integrated circuit, having all the inputs in one side, and all the outputs on the other side. This would permit centralized control for information access and selecting the appropriate input stream for the appropriate output stream. However, the monolithic integrated circuit approach is not realizable given the current limits of semiconductor fabrication technology and desirable switch size.
Once practical solution this problem is to distribute the switching function amongst an assembly of multiple switching chips, and referring to this assembly as a switch or a switching device within the switching fabric. In order to adequately function, connections must exist from every valid input to every valid output of the switching fabric. One distributed switch architecture which is utilized widely is today is called the “Clos Architecture,” developed by Charles Clos in 1953. This architecture, also known as the Clos switch, may be realized as a multistage, non-blocking network which has the advantage of reduced cost and complexity associated with other switches, such as the traditional crossbar switch.
A typical logical diagram of a Clos switch is a three-stage switch having inputs (ingress traffic) and outputs (egress traffic) as shown in FIG. 1. The first stage is divided into plurality of ingress switches, the second stage is plurality of center switches, and the third stage is plurality of output switches. Each stage contains one or more switching chips, and the sum total these chips produces the switching fabric which allows the direction of data from one input chip to a central stage chip to the appropriate output chip. The ingress and egress switches may be packaged into a plurality (Y) of ingress line modules 110 (LMs) and egress 120 LMs, while the center switches are packaged into a plurality (Z) of switch modules 115 (SMs). One of ordinary skill in the art would appreciate that the separate line modules shown in FIG. 1 are not necessarily physically distinct devices, and distinct modules are delineated merely as a function of their logical operation. The distinct functionally performed by ingress LMs 110 and egress LMs 120 may be realized on a single piece of hardware configured to operate in either (or more likely, both) mode(s), depending on the direction of the flow of data. Moreover, as shown in FIG. 1, LMs 110, 120 and SMs 115 are collectively divided into two vertical groups only for comparison with embodiments of the invention presented below.
Each ingress line module 110 should have at least one logical link to each switch module 115, and each egress line module 120 should have at least one logical link to each switch module 115. By logical link, it is meant that an information path exists between two devices so that the two devices can send and/or receive communications to and/or from each other. As used herein, the term “link” is used to refer to a physical link, such as a fiber optic line. Note that a physical link need not be equivalent to a logical link. For example, a physical link may comprise a plurality of logical links and/or a plurality of physical links may comprise a logical link.
Further referring to FIG. 1, ingress traffic, typically coming over one or more links such as fiber optic cables, enters ingress line modules 110. Line and section overhead data may be terminated at this point, and path overhead data may pass through ingress line module 110 as part of the data stream. Traffic may enter and proceed through ingress line modules 110, and travel across a plurality of logical links, each denoted as n1, to switch modules 115 (which may contain one or more switching chips). These logical links are realized as (physical) links which are formed on the backplane (not shown) supporting the switch fabric, and each logical link n1 depicted as a single line may consist of one or more links. From SM 115, traffic travels across n1 logical links through each egress LM 120, and then may exit through another link, such as, for example, one or more fiber optic cables.
Further referring to FIG. 1, because each of ingress LM 110 may be connected to SM 115, and each SM 115 may in turn be symmetrically connected to egress LM 120, a full complement of center stage switches may be needed in order for a large switching device to operate with full line module bandwidth. In other words, in order to properly make enough connections between all of the inputs and outputs to transport the data supplied by all the ports on each LM, the full complement of center stage switches may be needed in order to create a valid network for passing traffic. This condition may present limitations (such as undesirably high cost) in some low port-count applications when only a few input/output ports are required. As used herein, a port may be an external interface between a line module and a link used to transport data to and from the switch 100.
Typically, it is desirable to utilize common hardware whenever possible when realizing a network. Such benefits as reduced overall cost, streamlined maintenance and training, and higher system reliability are associated with hardware standardization. A customer desiring the benefits of standardizing switching equipment would have to purchase a full complement of center stage switches, even if the networking application is a low bandwidth one which may only using one or two line modules. Thus, an unnecessary additional expense is incurred by purchasing common equipment which may be underutilized for the low-bandwidth application.